1. Field of the Invention
The present invention relates to a vertical synchronizing circuit, or more specifically to a vertical synchronizing circuit of count-down type suitably embodied for TV receivers or the like used in an environment with varying electric field intensity.
2. Description of the Related Art
The TV receiver or the like operated in an environment with varying electric field intensity like a vehicle-mounted TV, as disclosed in Examined Patent Application JP-B2 59-15595 (1984) or Examined Patent Application JP-B2 60-42664 (1985), uses a vertical sync circuit of count-down type in order to stabilize the vertical scanning operation. For this purpose, a clock signal NfH having a frequency N times (N: a natural number of 2 or more) the frequency fH of the horizontal sync signal extracted from the input TV composite signal through a sync separator circuit is produced. This clock signal NfH is frequency-divided by a frequency divider in synchronism with the vertical sync sign. A frequency-divided signal having a frequency equal to the vertical sync signal is thus generated as a count-down vertical sync signal, and is applied to a vertical deflection circuit for vertical scanning.
In the NTSC system which is the standard TV system in Japan, for example, the frequency ratio fV/fH between the vertical sync signal VS and the horizontal sync signal HS contained in the TV composite signal is 60/15750=1/262.5. A vertical sync signal is therefore obtained by dividing the signal N times the frequency of the horizontal sync signal by N.times.262.5. In that process, in order to remove the instability sync elements such as drifts or jitters, a reference signal generator and a phase comparator are provided. A reference signal in synchronism with the vertical sync signal is generated by the reference signal generator on the basis of the horizontal sync signal, and the phase of the frequency-divided signal is compared with that of the reference signal by the phase comparator. When a phase drift is detected, a reset signal is output from the phase comparator to the frequency divider. In this way, a frequency-divided signal always in synchronism with the vertical sync signal is output as a count-down vertical sync signal thereby to perform stable vertical scanning operation free of jitters and drifts.
A typical prior art circuit is shown in the block diagram of FIG. 18. In FIG. 18, a TV receiving circuit 51 includes a tuner, an intermediate frequency amplifier, a detector and a video amplifier. A signal processing circuit 52 is for reproducing and amplifying a luminance signal and a chrominance signal A display device 53 is realized by display means such as a cathode-ray tube. A sync separator 54 is for separating and extracting the horizontal sync signal HS and the vertical sync signal VS from the TV composite signal applied thereto. The period of the vertical sync signal VS used for TV broadcasting is hereinafter referred to as the standard period (262.5 H, where H is the period of the horizontal sync signal HS).
A horizontal deflection circuit 55 is for electrically energizing the horizontal deflection coil HL, and a vertical deflection circuit 56 for electrically energizing the vertical deflection coil VL. These circuits are identical to those used for a common TV receiver. The vertical sync signal VS, however, is applied to a reference signal generator 63. A vertical sync circuit of count-down type (hereinafter referred to as "the vertical sync circuit") 71 includes a frequency doubler 61, a frequency divider 62, a reference signal generator 63 and a phase comparator 64.
The horizontal sync signal HS is applied to the frequency doubler 61 for generating a clock signal 2fH having a frequency (=31,500 Hz) twice that of the horizontal sync signal HS, which clock signal is applied to the frequency divider 62 and the reference signal generator 63. The clock signal 2fH is frequency-divided to 1/525 by flip-flops 62a to 62j and a NAND gate 62k in the frequency divider 62, and in synchronism with the vertical sync signal VS, a count-down vertical sync signal VD having a frequency equal to the frequency fV thereof is generated.
The reference signal generator 63 includes a reset signal circuit 63a having a D-type flip-flop and a NAND gate, a counter 63b having two stages of flip-flops, and a pulse generator 63c having a NAND gate and an R-S flip-flop. The clock signal 2fH and the vertical sync signal VS are applied to the reset signal circuit 63a thereby to generate a reset signal RC in synchronism with the vertical sync signal VS. The counter 63b is for counting the clock signal 2fH in synchronism with the vertical sync signal VS by the reset signal RC, and produces a counter pulse OC for each 262.5 H which is the standard period. The clock signal 2fH applied to the pulse generator 63c is gated by use of the counter pulse OC, so that the pulse generator 63c outputs a reference signal VR always in synchronism with the vertical sync signal VS.
The reference signal VR is compared with the count-down vertical sync signal VD in phase by the NAND gate of the phase comparator 64. In the case where the reference signal VR and the count-down vertical sync signal VD are out of phase, a reset signal RD is output from the phase comparator 64 and applied to the reset terminal R of the flip-flops 62a to 62j which constitutes the frequency divider 62. Thus the operation is performed for synchronizing the count-down vertical sync signal VD produced from the frequency divider 62 with the vertical sync signal VS. The reference signal VR used for this synchronization is generated on the basis of the clock signal 2fH having a frequency twice that of the horizontal sync signal HS and the vertical sync signal VS as described above. Therefore, a stable count-down vertical sync signal VD not affected by the receiving conditions of the TV signal, drift or jitter is obtained, thereby contributing to picture stabilization.
The conventional vertical sync circuit 71 described above, in which the period of the vertical sync signal VS is defined as the standard period of 262.5 H, is effective when supplied with the vertical sync signal VS for TV broadcasting. A problem of this conventional vertical sync circuit, however, is that an out-of-phase condition occurs with the periods for special VTR reproduction mode other than the standard periods such as in still image, slow reproduction or search mode.
In the case where a vertical sync signal having a non-standard period of 263.5 H is applied, for example, it is determined that the reference signal VR is overlapped in phase with the frequency-divided signal VD so that the frequency-divided signal VD of the standard period is applied to the vertical deflection circuit 56 during a given period. Subsequently, at a time point when the reference signal VR ceases to be contained in the pulse period of the frequency-divided signal. VD due to the out-of-phase condition, one of the flip-flops 62a to 62j of the frequency divider 62 is reset by the reference signal VR, with the result that the frequency-divided signal VD comes into phase with the vertical sync signal having a non-standard period of 263.5 H extracted at the sync separator 54. After that, the synchronization with the standard period occurs due to an out-of-phase condition. This series of operation is repeated. Consequently, the vertical synchronization becomes unstable with the display screen swinging vertically, for example.